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Data Sheet
VOLTAGE AND CURRENT READBACK
The ADM1191 contains the components to allow voltage and
current readback over an I 2 C bus. The voltage output of the
current sense amplifier and the voltage on the VCC pin are fed
into a 12-bit ADC via a multiplexer. The device can be instructed
to convert voltage and/or current at any time during operation
by issuing an I 2 C command or driving the CONV pin high. When
all conversions are complete, the voltage and/or current values
can be read back with 12-bit accuracy in two or three bytes.
SERIAL BUS INTERFACE
ADM1191
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the
low period before the ninth clock pulse, known as the
acknowledge bit, and holding it low during the high period
of this clock pulse. All other devices on the bus remain idle
while the selected device waits for data to be read from it
or written to it. If the R/W bit is 0, the master writes to the
slave device. If the R/W bit is 1, the master reads from the
slave device.
Control of the ADM1191 is carried out via the serial system
management bus (I 2 C). This interface is compatible with the I 2 C
fast mode (400 kHz maximum). The ADM1191 is connected to
this bus as a slave device, under the control of a master device.
IDENTIFYING THE ADM1191 ON THE I 2 C BUS
The ADM1191 has a 7-bit serial bus slave address. When the
device powers up, it does so with a default serial bus address.
The three MSBs of the address are set to 011; the four LSBs are
determined by the state of the A0 pin and the A1 pin. There are
16 configurations available on the A0 pin and A1 pin that corre-
spond to 16 I 2 C addresses for the four LSBs (see Table 5). This
scheme allows 16 ADM1191 devices to operate on a single I 2 C bus.
GENERAL I 2 C TIMING
Figure 16 and Figure 17 show timing diagrams for general write
and read operations using the I 2 C. The I 2 C specification defines
conditions for different types of read and write operations, which
are discussed in the Write and Read Operations section. The
general I 2 C protocol operates as follows:
2.
Data is sent over the serial bus in sequences of nine clock
pulses: eight bits of data followed by an acknowledge bit
from the slave device. Data transitions on the data line
must occur during the low period of the clock signal and
remain stable during the high period because a low-to-
high transition when the clock is high can be interpreted as
a stop signal.
If the operation is a write operation, the first data byte after
the slave address is a command byte. This tells the slave
device what to expect next. It can be an instruction, such as
telling the slave device to expect a block write, or it can be
a register address that tells the slave where subsequent data
is to be written.
Because data can flow in only one direction, as defined by
the R/W bit, it is not possible to send a command to a slave
device during a read operation. Before performing a read
operation, it may be necessary to first execute a write
operation to tell the slave what sort of read operation to
expect and/or the address from which data is to be read.
1.
The master initiates a data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line, SDA, while the serial clock line, SCL, remains high.
This indicates that a data stream is to follow. All slave periph-
erals connected to the serial bus respond to the start condition
and shift in the next eight bits, consisting of a 7-bit slave
address (MSB first) plus an R/W bit that determines the
direction of the data transfer, that is, whether data is written
to or read from the slave device (0 = write, 1 = read).
3.
When all data bytes are read or written, stop conditions are
established. In write mode, the master pulls the data line
high during the 10 th clock pulse to assert a stop condition.
In read mode, the master device releases the SDA line
during the SCL low period before the ninth clock pulse,
but the slave device does not pull it low. This is known as a no
acknowledge. The master then takes the data line low during
the SCL low period before the 10 th clock pulse and then high
during the 10 th clock pulse to assert a stop condition.
Table 5. Setting I 2 C Addresses via t he A0 Pin and the A 1 Pin
Base Address
011
A1 Pin State
Ground
Ground
Ground
Ground
Resistor to ground
Resistor to ground
Resistor to ground
Resistor to ground
Floating
Floating
A0 Pin State
Ground
Resistor to ground
Floating
High
Ground
Resistor to ground
Floating
High
Ground
Resistor to ground
A1 Pin Logic State
00
00
00
00
01
01
01
01
10
10
A0 Pin Logic State
00
01
10
11
00
01
10
11
00
01
Address in Binary 1
0110000X
0110001X
0110010X
0110011X
0110100X
0110101X
0110110X
0110111X
0111000X
0111001X
Address in Hex
0x60
0x62
0x64
0x66
0x68
0x6A
0x6C
0x6E
0x70
0x72
Rev. C | Page 9 of 16
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